1. Field of the Invention
The present invention relates to a dual port semiconductor memory device and, particularly, to a dual port random access memory (RAM) having a write-per-bit function in which memory cells are read serially and written randomly.
2. Description of the Prior Art
A dual port DRAM to be arranged between a CPU of a compact computer such as personal computer and a data display device for displaying read/write under control of the CPU is commercially available and has been used widely for image processing purpose. Such dual port RAM includes input/output buffer circuits capable of storing a plurality of bits to realize functions such as serial data transfer function and flush clear function, etc. A dual port RAM having such construction as above mentioned is disclosed in U.S. Pat. No. 4,669,064 issued to Ishimoto and assigned to the assignee of this application. In the disclosed dual port RAM, in order to improve image processing speed and flexibility, a memory information is read in time-serial from the input/output buffer circuits through serial ports and a memory information is written randomly through an arbitrary stage of the input/output buffer circuits. The above mentioned write operation of memory information is referenced to as "write-per-bit" function.
Describing the write-per-bit function in more detail, the dual port RAM with write-per-bit function disclosed in Ishimoto '064 comprises a memory cell array composed of a plurality of memory cells each arranged at each of intersections of a plurality of rows or bit lines, and a plurality of columns or word lines, means responsive to a row address signal for selecting one of the bit lines, a plurality of bus lines, means responsive to a column address signal for selectively connecting the bus lines to the same number of the columns or word lines, respectively, a plurality of data input/output terminals, a plurality of input/output buffer circuits having input sides connected to the respective data input/output terminals and output sides connected to the bus lines for holding data from the data input/output terminals during a write cycle, a plurality of write-inhibit signal detection circuits arranged correspondingly to the data input/output terminals for detecting presence or absence of a write inhibit signal to be supplied at a start time of the write cycle and a plurality of control circuits provided correspondingly to the respective input/output buffer circuits to disable the input/output buffer circuits when the detection circuits detect write inhibit signals, and only data stored in the input/output buffer circuits which are not inhibited by the write inhibit signal can be written in the memory cells during the write cycle.
The dual port RAM with write-per-bit function has not only its inherent functions, that is, functions of simultaneous read of a plurality of bits, for example, 4 bits, by random access and of serial read of multi words (4 bits.times.64K words) by serial access, but also the function of random write from serial ports for arbitrary bits. Therefore, such RAM is more suitably adapted to the image processing.
On the other hand, with an improvement of semiconductor manufacturing technology to make integration density of a semiconductor chip higher, an area of the semiconductor chip to be occupied by each memory cell was reduced, so that memory capacity of a memory cell array was increased substantially. Indeed, memory capacity of an RAM was increased from 256K bits through 1M bits to 4M bits in recent several years. In order to prevent increase of peak current and decrease of operation speed of the memory cell array due to increased memory capacity thereof, a layout of the memory cell array on the semiconductor chip becomes important, since bit lines and word lines become longer, signal delay occurs due to increased resistance of the long word lines and signal amount is reduced due to increase of stray capacitance of the longer bit lines. For example, in T. Watanabe, "A Battery Backup 64K CMOS RAM with Double Level Aluminum Technology", ISSC DIGEST OF TECHNICAL PAPERS, Feb. 1983, pp 60-61, it is proposed, in order to solve such problems, to divide a memory cell array forming area of a semiconductor chip into a plurality of blocks. After Watanabe's proposal, the number of blocks is increased beyond that required for a dual port RAM having memory capacity of 256K bits and, thus, data signal lines, that is, word lines, of the memory cell array for data read/write becomes complicated and longer.
On the other hand, in a dual port RAM for image processing in an engineering work station (EWS), bit length of a unit code word becomes longer. Recently, there is commercially available dual port RAMs having bit length of 16 bits. By increasing bit length, the number of the data input/output terminals on the memory chip as well as the number of stages of the data holding means connected to the respective terminals can be increased. However, even in the memory circuit described in the Watanabe article, the balance of characteristics of transistors constituting data signal lines extending from the input/output buffer circuits to the memory cells can not be maintained at a desired level and the stray capacitance problem due to long data signal lines from the input/output buffer circuits to the memory cells can not be solved sufficiently. Further, the signal delay due to long word lines occur in a signal write, memory write speed is substantially lowered and an erroneous operation may occur due to cross-talk among multi bit word lines.